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CD4051B, CD4052B, CD4053B
Semiconductor
August 1998
File Number 902.2
CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD -VSS = 3V, a VDD -VEE of up to 13V can be controlled; for VDD -VDD level differences above 13V, a VDD -VDD of at least 4.5V is required). For example, if VDD = +4.5V, VDD = 0V, and VDD = -13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD -VDD and VDD -VDD supply-voltage ranges, independent of the logic state of the control signals. When a logic "1" is present at the inhibit input terminal, all channels are off. The CD4051B is a single 8-Channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw configuration. When these devices are used as demultiplexers, the "CHANNEL IN/OUT" terminals are the outputs and the "COMMON OUT/IN" terminals are the inputs.
Features
* Wide Range of Digital and Analog Signal Levels - Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V - Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VP-P * Low ON Resistance, 125 (Typ) Over 15VP-P Signal Input Range for VDD -VEE = 18V * High OFF Resistance, Channel Leakage of 100pA (Typ) at VDD -VEE = 18V * Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD -VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD -VEE = 20V) * Matched Switch Characteristics, rON = 5 (Typ) for VDD -VEE = 15V * Very Low Quiescent Power Dissipation Under All DigitalControl Input and Supply Conditions, 0.2W (Typ) at VDD -VSS = VDD -VEE = 10V * Binary Address Decoding on Chip * 5V, 10V and 15V Parametric Ratings * 10% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC * Break-Before-Make Switching Eliminates Channel Overlap
Applications
* Analog and Digital Multiplexing and Demultiplexing * A/D and D/A Conversion * Signal Gating
Ordering Information
PART NUMBER CD4051BF, CD4052BF, CD4053BF CD4051BE, CD4052BE, CD4053BE CD4051BM, CD4052BM, CD4053BM TEMP. RANGE (oC) -55 to 125 PACKAGE PKG. NO.
16 Ld CERDIP F16.3
-55 to 125
16 Ld PDIP
E16.3
-55 to 125
16 Ld SOIC
M16.15
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1998
CD4051B, CD4052B, CD4053B Pinouts
CD4051B (PDIP, CERDIP, SOIC) TOP VIEW
41 62 16 VDD 15 2 14 1 CHANNELS IN/OUT CHANNELS IN/OUT 74 55 INH 6 VEE 7 VSS 8 13 0 12 3 11 A 10 B 9C Y CHANNELS IN/OUT 34 15 INH 6 VEE 7 VSS 8 13 COMMON "X" OUT/IN 12 0 11 3 10 A 9B X CHANNELS IN/OUT
CD4052B (PDIP, CERDIP) TOP VIEW
01 22 16 VDD 15 2 14 1 X CHANNELS IN/OUT
CHANNELS IN/OUT
Y CHANNELS IN/OUT
COM OUT/IN 3
COMMON "Y" OUT/IN 3
CD4053B (PDIP, CERDIP) TOP VIEW
by 1 IN/OUT bx 2 cy 3 OUT/IN CX OR CY 4 IN/OUT CX 5 INH 6 VEE 7 VSS 8 16 VDD 15 OUT/IN bx OR by 14 OUT/IN ax OR ay 13 ay 12 ax 11 A 10 B 9C IN/OUT
Functional Block Diagrams
CD4051B
CHANNEL IN/OUT 7 16 VDD 4 6 2 5 5 4 1 3 12 2 15 1 14 0 13 TG
TG A
11 TG COMMON OUT/IN 3 TG
B
10 LOGIC LEVEL CONVERSION
C
9
BINARY TO 1 OF 8 DECODER WITH INHIBIT
TG
TG
TG INH
6 TG
8 VSS
7 VEE
2
CD4051B, CD4052B, CD4053B Functional Block Diagrams
(Continued) CD4052B
X CHANNELS IN/OUT 3 11 2 15 1 14 0 12
TG 16 VDD TG TG TG A B INH
COMMON X OUT/IN 13 3 COMMON Y OUT/IN

10 9 6 LOGIC LEVEL CONVERSION
BINARY TO 1 OF 4 DECODER WITH INHIBIT
TG TG TG TG 1 0 5 1 2 2 4 3
8 VSS
7
VEE
Y CHANNELS IN/OUT
CD4053B
BINARY TO 1 OF 2 DECODERS WITH INHIBIT
LOGIC LEVEL CONVERSION
IN/OUT cy 5 cx 1 by 12 bx 15 ay 14 ax 13 TG COMMON OUT/IN ax OR ay 14
16 VDD
A
11
TG COMMON OUT/IN bx OR by 15
TG B
10
TG COMMON OUT/IN cx OR cy 4 TG
C
9
TG
INH
6
VDD
8
VSS
7
VEE
All inputs protected by standard CMOS protection network
3
CD4051B, CD4052B, CD4053B
TRUTH TABLES INPUT STATES INHIBIT CD4051B 0 0 0 0 0 0 0 0 1 CD4052B INHIBIT 0 0 0 0 1 CD4053B INHIBIT 0 0 1 X = Don't Care A OR B OR C 0 1 X ax or bx or cx ay or by or cy None B 0 0 1 1 X A 0 1 0 1 X 0x, 0y 1x, 1y 2x, 2y 3x, 3y None 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 X 0 1 2 3 4 5 6 7 None C B A "ON" CHANNEL(S)
4
CD4051B, CD4052B, CD4053B
Absolute Maximum Ratings Supply Voltage (V+ to V-) Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . 10mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A CERDIP Package. . . . . . . . . . . . . . . . . 115 45 SOIC Package . . . . . . . . . . . . . . . . . . . 115 N/A Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified (Note 3) CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC) 25
PARAMETER
VIS (V)
VEE (V)
VSS (V)
VDD (V)
-55
-40
85
125
MIN
TYP
MAX
UNITS
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS) Quiescent Device Current, IDD Max Drain to Source ON Resistance rON Max 0 VIS VDD Change in ON Resistance (Between Any Two Channels), rON OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max) Capacitance: Input, CIS Output, COS CD4051 CD4052 CD4053 Feedthrough CIOS Propagation Delay Time (Signal Input to Output VDD RL = 200k, CL = 50pF, tr , tf = 20ns 5 10 15 0.2 30 15 10 60 30 20 pF ns ns ns 30 18 9 pF pF pF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 10 15 20 5 10 15 5 10 15 18 5 10 20 100 800 310 200 5 10 20 100 850 330 210 150 300 600 3000 1200 520 300 150 300 600 3000 1300 550 320 0.04 0.04 0.04 0.08 470 180 125 15 10 5 0.01 5 10 20 100 1050 400 240 100 (Note 2) A A A A A
100 (Note 2)
1000 (Note 2)
-
-5
5-
5 5 pF
5
CD4051B, CD4052B, CD4053B
Electrical Specifications
Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified (Continued) (Note 3) CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC) 25 PARAMETER VIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS
CONTROL (ADDRESS OR INHIBIT), VC VIL = VDD through 1k; VIH = VDD through Input High Voltage, VIH , 1k Min Input Low Voltage, VIL , Max VEE = VSS , RL = 1k to VSS , IIS < 2A on All OFF Channels 5 10 15 5 10 15 Input Current, IIN (Max) Propagation Delay Time: Address-to-Signal tr , tf = 20ns, OUT (Channels ON or CL = 50pF, OFF) See Figures 10, RL = 10k 11, 14 0 0 0 -5 Propagation Delay Time: Inhibit-to-Signal OUT tr , tf = 20ns, (Channel Turning ON) CL = 50pF, See Figure 11 RL = 1k 0 0 0 -10 Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning OFF) See Figure 15 tr , tf = 20ns, CL = 50pF, RL = 10k 0 0 0 -10 Input Capacitance, CIN (Any Address or Inhibit Input) NOTE: 2. Determined by minimum feasible leakage measurement for automatic testing. 0 0 0 0 5 10 15 5 200 90 70 130 5 450 210 160 300 7.5 ns ns ns ns pF 0 0 0 0 5 10 15 5 400 160 120 200 720 320 240 400 ns ns ns ns 0 0 0 0 5 10 15 5 450 160 120 225 720 320 240 450 ns ns ns ns VIN = 0, 18 18 1.5 3 4 3.5 7 11 0.1 1.5 3 4 3.5 7 11 0.1 1.5 3 4 3.5 7 11 1 1.5 3 4 3.5 7 11 1 3.5 7 11 10-5 1.5 3 4 0.1 V V V V V V A
Electrical Specifications
TEST CONDITIONS PARAMETER Cutoff (-3dB) Frequency Channel ON (Sine Wave Input) VIS (V) 5 (Note 3) VEE = VSS , V OS 20Log ----------- = - 3dB V IS VDD (V) 10 RL (k) 1 VOS at Common OUT/IN CD4053 CD4052 CD4051 VOS at Any Channel LIMITS TYP 30 25 20 60 UNITS MHz MHz MHz MHz
6
CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS PARAMETER Total Harmonic Distortion, THD VIS (V) 2 (Note 3) 3 (Note 3) 5 (Note 3) VDD (V) 5 10 15 RL (k) 10 LIMITS TYP 0.3 0.2 0.12 UNITS % % % % VOS at Common OUT/IN CD4053 CD4052 CD4051 VOS at Any Channel Between Any 2 Channels Between Sections, CD4052 Only Measured on Common Measured on Any Channel In Pin 2, Out Pin 14 In Pin 15, Out Pin 14 8 10 12 8 3 6 10 2.5 6 65 65 MHz MHz MHz MHz MHz MHz MHz MHz MHz mVPEAK mVPEAK
VEE = VSS, fIS = 1kHz Sine Wave -40dB Feedthrough Frequency (All Channels OFF) 5 (Note 3) VEE = VSS , V OS 20Log ----------- = - 40dB V IS -40dB Signal Crosstalk Frequency 5 (Note 3) VEE = VSS , V OS 20Log ----------- = - 40dB V IS 10 1 10 1
Between Any Two Sections, CD4053 Only Address-or-Inhibit-to-Signal Crosstalk 10 10 (Note 4)
VEE = 0, VSS = 0, tr , tf = 20ns, VCC = VDD - VSS (Square Wave) NOTES: 3. Peak-to-Peak voltage symmetrical about 4. Both ends of channel. V DD - V EE ----------------------------2
Typical Performance Curves
600 rON , CHANNEL ON RESISTANCE () rON , CHANNEL ON RESISTANCE () VDD - VEE = 5V 500 300 VDD - VEE = 10V 250 TA = 125oC
400 TA = 125oC TA = 25oC TA = -55oC 100
200
300
150 TA = 25oC 100 TA = -55oC 50
200
0 -4 -3 -2 -1 0 1 2 3 4 5 VIS , INPUT SIGNAL VOLTAGE (V)
0 -10
-7.5
-5 -2.5 0 2.5 5 VIS , INPUT SIGNAL VOLTAGE (V)
7.5
10
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)
FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)
7
CD4051B, CD4052B, CD4053B Typical Performance Curves
600 rON , CHANNEL ON RESISTANCE () 500 400 300 200 10V 100 0 -10 15V VDD - VEE = 5V rON , CHANNEL ON RESISTANCE () TA = 25oC
(Continued)
250 VDD - VEE = 15V 200 TA = 125oC
150 TA = 25oC TA = -55oC 50
100
-7.5
-5
-2.5
0
2.5
5
7.5
10
0 -10
-7.5
-5
-2.5
0
2.5
5
7.5
10
VIS , INPUT SIGNAL VOLTAGE (V)
VIS , INPUT SIGNAL VOLTAGE (V)
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)
6 VOS , OUTPUT SIGNAL VOLTAGE (V) VDD = 5V VSS = 0V VEE = -5V TA = 25oC RL = 100k, RL = 10k 1k 500 100
FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)
105
PD , POWER DISSIPATION PACKAGE (W)
4
TA = 25oC ALTERNATING "O" AND "I" PATTERN CL = 50pF 104 VDD = 15V
TEST CIRCUIT VDD f B/D CD4029 ABC
2
0
103 VDD = 10V VDD = 5V CL = 15pF 1 10
-2 -4 -6
102
VDD 100 11 10 9 13 14 15 12 CD4051 1 5 3 2 48 7 6 C L 100
105
-6
-4
-2 0 2 4 VIS , INPUT SIGNAL VOLTAGE (V)
6
10
102 103 104 SWITCHING FREQUENCY (kHz)
FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS (CD4051B)
FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4051B)
PD , POWER DISSIPATION PACKAGE (W)
PD , POWER DISSIPATION PACKAGE (W)
105
104
TA = 25oC ALTERNATING "O" AND "I" PATTERN CL = 50pF VDD = 15V
105
103 VDD = 10V 102 VDD = 5V CL = 15pF 10 1 10
CD4029 VDD B/D AB 100 10 9 1 3 CL 13 5 12 2 4 CD4052 14 15 6 11 7 8
f
TEST CIRCUIT VDD
104
TA = 25oC ALTERNATING "O" AND "I" PATTERN CL = 50pF
VDD = 15V VDD = 10V TEST CIRCUIT VDD f 9 4 CL 100 3 12 5 13 100 CD4053 2 10 1 15 11 14 6 7 8
103
100
102
VDD = 5V CL = 15pF
105
10 1 10 102 103 104 SWITCHING FREQUENCY (kHz) 105
102 103 104 SWITCHING FREQUENCY (kHz)
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4052B)
FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4053B)
8
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms
VDD = 15V VDD = 7.5V VDD = 5V VDD = 5V
7.5V 16 16
5V
5V
16 VSS = 0V VSS = 0V
16
VSS = 0V VEE = 0V VSS = 0V
(A) (B) (C) (D)
7 8
VEE = -7.5V
7 8
VEE = -10V
7 8
VEE = -5V
7 8
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: "0" = VSS and "1" = VDD. The analog signal (through the TG) may swing from VEE to VDD. FIGURE 9. TYPICAL BIAS VOLTAGES
tr = 20ns 90% 50% 10% TURN-ON TIME 90% 50% 10% TURN-OFF TIME 90% 50%
tf = 20ns
tr = 20ns 90% 50% 90% 50%
tf = 20ns
10%
10%
10%
90% 10% TURN-OFF TIME tPHZ 10% TURN-ON TIME
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON (RL = 1k)
FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF (RL = 1k)
VDD
VDD
VDD
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 CD4051
IDD
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 CD4052
IDD
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 CD4053
IDD
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF
9
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued)
VDD VDD VDD
IDD
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 CD4051
IDD
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 CD4052
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 CD4053
IDD
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
OUTPUT
OUTPUT 16 15 14 13 12 11 10 9 CD4052 VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CD4053
VDD OUTPUT RL CL VEE
VDD
VEE VSS
CD4051
VSS
1 RL CL 2 RL CL 3 VDD VEE 4 VDD 5 VEE 6 VEE VSS CLOCK 7 IN 8 VSS
VDD
VEE
VDD
VSS CLOCK VSS IN VSS
VSS CLOCK IN VSS
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
OUTPUT RL 50pF VEE VDD VSS VDD CLOCK VEE IN VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VDD
OUTPUT RL 50pF VEE VDD VSS VDD CLOCK VEE IN VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VDD
OUTPUT RL 50pF VEE VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD
VDD VSS CLOCK VEE IN VSS
tPHL AND tPLH VSS CD4051
V tPHL AND tPLH SS CD4052
V tPHL AND tPLH SS CD4053
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
VDD A 1K 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VIL VDD VIH 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1K A VIH VIL VIH VIL MEASURE < 2A ON ALL "OFF" CHANNELS (e.g., CHANNEL 2x) MEASURE < 2A ON ALL "OFF" CHANNELS (e.g., CHANNEL by) 1K 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 A VDD
1K
VIH VIL
1K
VIH VIL
1K
VIH VIL
CD4051B
CD4052B
CD4053B
MEASURE < 2A ON ALL "OFF" CHANNELS (e.g., CHANNEL 6)
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
10
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued)
VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VDD KEITHLEY 160 DIGITAL MULTIMETER TG "ON" 1k RANGE
10k
Y X-Y PLOTTER
VSS
CD4051 CD4053
CD4052
H.P. MOSELEY 7030A
X
FIGURE 17. QUIESCENT DEVICE CURRENT
FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT CIRCUIT
VDD 1 2 3 4 5 6 7 8 VSS 16 15 14 13 12 11 10 9 CD4051 CD4053 1 2 3 4 5 6 7 8 VSS 16 15 14 13 12 11 10 9 CD4052
VDD
VDD VSS
VDD VSS
NOTE: Measure inputs sequentially, to both VDD and VSS connect all unused inputs to either VDD or VSS .
NOTE: Measure inputs sequentially, to both VDD and VSS connect all unused inputs to either VDD or VSS .
FIGURE 19. INPUT CURRENT
CHANNEL ON 5VP-P VDD 6 7 8 OFF CHANNEL RF VM 1K CHANNEL OFF RL RF VM COMMON RL
5VP-P
CHANNEL OFF
RF VM
RL CHANNEL ON RL
FIGURE 20. FEEDTHROUGH (ALL TYPES)
FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS (ALL TYPES)
5VP-P
CHANNEL IN X ON OR OFF RL
CHANNEL IN Y ON OR OFF RL
RF VM
FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)
11
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued)
DIFFERENTIAL SIGNALS CD4052 CD4052
COMMUNICATIONS LINK
DIFF. AMPLIFIER/ LINE DRIVER
DIFF. RECEIVER
DIFF. MULTIPLEXING
DEMULTIPLEXING
FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B
Special Considerations
In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.
A B C
A B CD4051B C INH Q0 1/2 CD4556 Q1 Q2 COMMON OUTPUT
D E
A B E
A B CD4051B C INH
A B CD4051B C INH
FIGURE 24. 24-TO-1 MUX ADDRESSING
12
CD4051B, CD4052B, CD4053B Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
13
CD4051B, CD4052B, CD4053B Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
14
CD4051B, CD4052B, CD4053B Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
A1 B C D
A1 0.10(0.004) C
E e H h L N
e
B 0.25(0.010) M C AM BS
0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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